In traditional semiconductor manufacturing processes of a local interconnect structure, in particularly, in a manufacturing process of a local interconnect structure of a fin field-effect transistor (FinFET) device, due to the small feature size and high density of the integration, requirements on the manufacturing process can be relatively high. For example, for a local interconnect structure of a FinFET device of technology nodes below 20 nm, due to technology constraints of current lithography processes, the formation of a small-size local interconnect structure may require a double patterning lithography (double exposure lithography) process which involves complicated process steps and imposes relatively high technology requirements.
FIG. 1 is a plan view of an exemplary FinFET device 100 having a local interconnect structure that can be used to explain the principles of the present invention. Device 100 includes multiple fins 101, multiple gates 102, a first interconnect layer 103, a second interconnect layer 104, and a gate interconnect layer 105. Double patterning lithography may be required for technology nodes below 20 nm. A double patterning lithography process may include performing a first etching process using a first mask to form a trench in first interconnect layer 103, then performing a second etching process using a second mask to form a trench in second interconnect layer 104. Thereafter, a metal silicide layer is formed at the bottom of the trench of first interconnect layer 103 and at the bottom of the trench of second interconnect layer 104. Next, a third etching process is performed to form a trench in gate interconnect layer 105 using a mask, and a metal layer is deposited to fill each of the trenches and to form a local interconnect structure. As can be seen in the conventional technique, the trench in first interconnect layer 103 and the trench in second interconnect layer 104 are formed separately, and the accuracy requirements on the patterned mask and on the etching coverage are high, which impose a challenge in the manufacturing process of a local interconnect structure of technology nodes below 20 nm.